EU projects: starting REPARA

EU projects: 3.5 M€ REPARA (EC-STREP, 7th FP): Reengineering and Enabling Performance And poweR of Applications (2013, 36 months).

In recent years, traditional processors have not been able to translate the advances of silicon fabrication technology into corresponding performance gains. This has been due to weaknesses inherent in the current sequential programming model, which has not changed significantly since the late 1940’s, as well as due to physical constraints, such as practical limits on the energy consumption and the associated cooling efforts for a processor. To keep satisfying the ever-growing demand for computing power, these difficulties have forced a shift from homogeneous machines relying on a one single kind of fast processing element (the CPU) such as typical PCs some years ago, programmed mostly sequentially, to heterogeneous architectures combining different kinds of processors (such as CPUs, GPUs and DSPs) each specialized for certain tasks, and programmed in a highly parallel fashion yet poorly optimising the available resources towards performance and low energy consumption.

The REPARA project joins forces of experts in software engineering methodology, development tools, computer hardware design and analysis, all working hand-in-hand with industrial end-users to achieve a unified programming model for heterogeneous computers developing also the required automated software support tools. Relative to the base line of a sequential algorithm executed on a current general-purpose processor, REPARA expects to achieve at least a 50% reduction of energy consumption combined with a performance improvement of at least by a factor of two. REPARA will also allow for an increased productivity realizing designs in half of the development time that would be required using non-unified programming methods for the different components of a heterogeneous system. Combined, REPARA will lead to fourfold gain in efficiency for energy savings and performance. These objectives will be verified in 5 real-world use cases in the domains of railway, healthcare and industrial maintenance and robotics.

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About Marco Aldinucci

Marco Aldinucci is an assistant professor at Computer Science Department of the University of Torino since 2008. Previously, he has been researcher at University of Pisa and Italian National Research Agency. He is the author of over a hundred papers in international journals and conference proceeding (Google scholar h-index 21). He has been participating in over 20 national and international research projects concerning parallel and autonomic computing. He is the recipient of the HPC Advisory Council University Award 2011 and the NVidia Research award 2013. He has been leading the “Low-Level Virtualization and Platform-Specific Deployment” workpackage within the EU-STREP FP7 ParaPhrase (Parallel Patterns for Adaptive Heterogeneous Multicore Systems) project, the GPGPU workpackage within the IMPACT project (Innovative Methods for Particle Colliders at the Terascale), and he is the contact person for University of Torino for the European Network of Excellence on High Performance and Embedded Architecture and Compilation. In the last year he delivered 5 invited talks in international workshops (March 2012 – March 2013). He co-designed, together with Massimo Torquati, the FastFlow programming framework and several other programming frameworks and libraries for parallel computing. His research is focused on parallel and distributed computing.